Lithography Optimization for Sub - 22 Nanometer Technologies

Continuing scaling of complementary metal-oxidesemiconductor (CMOS) is crucial for the electronic industry because an integrated circuit (IC) with a smaller feature size can provide a smaller silicon area, lower power consumption, higher performance, cheaper price, etc. As the IC process nodes continue to shrink to 22nm and below, the IC industry will face severe manufacturing challenges with conventional optical lithography technologies. According to recent surveys, three most expected technologies may push the limits of lithography: multiple patterning lithography (MPL), electron beam lithography (EBL) and extreme ultraviolet lithography (EUVL). However, each of which encounters different design difficulties and requires solutions for breakthroughs. In this study, we investigate the most critical design challenges of the three technologies: the layout decomposition problem in MPL, the accumulated heating problem in EBL, and the flare effect in EUVL. To overcome these challenges, we transform the original problems into corresponding optimization problems and develop novel algorithms to solve these problems. Experimental results show that the proposed algorithms can efficiently and effectively generate good layout decomposition solutions for MPL, mitigate the thermal problem in EBL, and alleviate flare level and flare variation in EUVL. These results not only can enhance process manufacturability, but also can contribute to the continuing scaling of the CMOS technology.